[ DevCourseWeb.com ] Udemy - VLSI - Essential concepts and detailed interview guide

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~Get Your Files Here !/01 - Physical Design Flow Overview/004 Route - DRC Clean - Parasitics Extraction - Final STA.mp4 106.1 MB
~Get Your Files Here !/16 - Routing And Design Rule Check (DRC)/002 Design Rule Check.mp4 99.5 MB
~Get Your Files Here !/03 - Placement/002 Optimize Placement Using Estimated Wire Length And Capacitance.mp4 91.4 MB
~Get Your Files Here !/16 - Routing And Design Rule Check (DRC)/001 Introduction To Maze Routing - Lee's Algorithm.mp4 88.2 MB
~Get Your Files Here !/03 - Placement/003 Optimize Placement Continued.mp4 87.0 MB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/004 Data Slew Check.mp4 82.9 MB
~Get Your Files Here !/17 - Parasitics Extraction/001 Introduction To IEEE 1481-1999 SPEF Format.mp4 78.5 MB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/003 Multiple Clock Timing Analysis And Introduction To Data Slew Check.mp4 72.8 MB
~Get Your Files Here !/15 - Noise Protection Technique/003 Drive Strength.mp4 67.6 MB
~Get Your Files Here !/01 - Physical Design Flow Overview/002 Netlist Binding And Placement Optimization.mp4 65.5 MB
~Get Your Files Here !/08 - Buffered H-Tree/004 H-Tree Clock Buffers And Pulse Width Check.mp4 65.5 MB
~Get Your Files Here !/08 - Buffered H-Tree/003 CMOS Inverter PMOSNMOS Matching Switching Resistance Solution.mp4 63.7 MB
~Get Your Files Here !/01 - Physical Design Flow Overview/003 Clock Net Shielding.mp4 62.8 MB
~Get Your Files Here !/08 - Buffered H-Tree/001 H-Tree Buffering Observations.mp4 60.5 MB
~Get Your Files Here !/08 - Buffered H-Tree/005 Dynamic Power And Short Circuit Power.mp4 58.3 MB
~Get Your Files Here !/11 - Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP/002 Dominant Lateral Capacitance.mp4 57.3 MB
~Get Your Files Here !/10 - Static Timing Analysis With Real Clocks/003 Impact Of Unbalanced Skew On Hold Time.mp4 55.7 MB
~Get Your Files Here !/06 - H-Tree/003 H-Tree Latency And Power Check.mp4 55.6 MB
~Get Your Files Here !/10 - Static Timing Analysis With Real Clocks/002 Impact Of Unbalanced Skew On Setup Time.mp4 52.8 MB
~Get Your Files Here !/06 - H-Tree/002 H-Tree Pulse Width And Duty Cycle Check.mp4 48.5 MB
~Get Your Files Here !/07 - Clock Tree Modelling and Observations/003 Clock Tree Observations.mp4 48.3 MB
~Get Your Files Here !/03 - Placement/001 Netlist Binding And Placement.mp4 46.4 MB
~Get Your Files Here !/02 - Floorplanning/004 Pin Placement And Logical Cell Placement Blockage.mp4 46.2 MB
~Get Your Files Here !/02 - Floorplanning/003 Power Planning.mp4 45.6 MB
~Get Your Files Here !/08 - Buffered H-Tree/002 H-Tree Pulse Width Check And Issues With Regular Buffers.mp4 45.5 MB
~Get Your Files Here !/01 - Physical Design Flow Overview/001 Floor-Planning Steps.mp4 45.5 MB
~Get Your Files Here !/14 - Crosstalk Delta Delay Analysis/004 Impact Of Crosstalk Delta Delay On Hold Timing.mp4 43.6 MB
~Get Your Files Here !/17 - Parasitics Extraction/002 SPEF Header Description, Physical Design Flow Conclusion And What Next !!.mp4 41.7 MB
~Get Your Files Here !/07 - Clock Tree Modelling and Observations/002 Clock Tree Building.mp4 39.4 MB
~Get Your Files Here !/14 - Crosstalk Delta Delay Analysis/002 Setup Timing Analysis Using Real Clocks.mp4 38.6 MB
~Get Your Files Here !/12 - Glitch Examples And Factors Affecting Glitch Height/004 Factors Affecting Glitch Height - Conclusion.mp4 36.1 MB
~Get Your Files Here !/12 - Glitch Examples And Factors Affecting Glitch Height/002 Glitch Discharge With High Drive Strength PMOS Transistor.mp4 34.9 MB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/002 Setup Timing Analysis With Multiple Clocks.mp4 34.3 MB
~Get Your Files Here !/12 - Glitch Examples And Factors Affecting Glitch Height/003 Factors Affecting Glitch Height - Aggressor Drive Strength.mp4 33.2 MB
~Get Your Files Here !/11 - Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP/003 Noise Margin Voltage Parameters.mp4 32.5 MB
~Get Your Files Here !/10 - Static Timing Analysis With Real Clocks/001 Static Timing Analysis With Real Clocks.mp4 32.0 MB
~Get Your Files Here !/05 - Clock Tree Synthesis - Introduction And Quality Check Parameters/004 Power And Crosstalk Quality Check.mp4 32.0 MB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/001 Setup Time Analysis And Introduction To Flip-Flop Setup Time.mp4 31.5 MB
~Get Your Files Here !/09 - Clock Tree Optimization Checklist/003 Optimized Clock Tree Power And Latency Check.mp4 30.9 MB
~Get Your Files Here !/05 - Clock Tree Synthesis - Introduction And Quality Check Parameters/003 Latency And Power Check.mp4 30.7 MB
~Get Your Files Here !/11 - Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP/004 Lower Supply Voltage.mp4 29.4 MB
~Get Your Files Here !/12 - Glitch Examples And Factors Affecting Glitch Height/001 Basic Crosstalk Glitch Example.mp4 29.2 MB
~Get Your Files Here !/02 - Floorplanning/002 Concept of Pre-placed Cells.mp4 28.8 MB
~Get Your Files Here !/02 - Floorplanning/001 Utilization Factor And Aspect Ratio.mp4 28.5 MB
~Get Your Files Here !/14 - Crosstalk Delta Delay Analysis/001 Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction.mp4 28.0 MB
~Get Your Files Here !/13 - Tolerable Glitch Heights and Introduction to AC Noise Margin/004 Justification Of Load Impact And Conclusion.mp4 27.9 MB
~Get Your Files Here !/13 - Tolerable Glitch Heights and Introduction to AC Noise Margin/003 AC Noise Margin.mp4 27.5 MB
~Get Your Files Here !/15 - Noise Protection Technique/002 Spacing.mp4 26.6 MB
~Get Your Files Here !/13 - Tolerable Glitch Heights and Introduction to AC Noise Margin/002 Tolerable Glitch Heights Using DC Noise Margin.mp4 26.6 MB
~Get Your Files Here !/09 - Clock Tree Optimization Checklist/002 Leakage Current Reduction Technique.mp4 26.3 MB
~Get Your Files Here !/09 - Clock Tree Optimization Checklist/001 Optimization Checklist.mp4 26.2 MB
~Get Your Files Here !/13 - Tolerable Glitch Heights and Introduction to AC Noise Margin/001 Impacts Of Glitch.mp4 25.9 MB
~Get Your Files Here !/05 - Clock Tree Synthesis - Introduction And Quality Check Parameters/002 Duty Cycle And Latency Check.mp4 25.0 MB
~Get Your Files Here !/15 - Noise Protection Technique/001 Shielding.mp4 24.9 MB
~Get Your Files Here !/07 - Clock Tree Modelling and Observations/001 Clock Tree Modelling.mp4 24.9 MB
~Get Your Files Here !/14 - Crosstalk Delta Delay Analysis/003 Crosstalk Delta Delay - Aggressor Victim Switching In Same Direction.mp4 24.3 MB
~Get Your Files Here !/06 - H-Tree/001 H-Tree Algorithm And Skew Check.mp4 22.3 MB
~Get Your Files Here !/05 - Clock Tree Synthesis - Introduction And Quality Check Parameters/001 Introduction To Clock Tree Synthesis.mp4 21.6 MB
~Get Your Files Here !/11 - Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP/001 Introduction.mp4 18.6 MB
~Get Your Files Here !/05 - Clock Tree Synthesis - Introduction And Quality Check Parameters/005 Glitch Quality Check.mp4 16.9 MB
~Get Your Files Here !/19 - BASICS OF MOS TRANSISTOR/004 IMPACT OF SUBSTRATE POTENTIAL ON THRESHOLD VOLTAGE (VT).mp4 11.6 MB
~Get Your Files Here !/19 - BASICS OF MOS TRANSISTOR/003 N-CHANNEL FORMATION BETWEEN SOURCE AND DRAIN.mp4 11.5 MB
~Get Your Files Here !/20 - SETUP & HOLD TIMING ANALYSIS/003 INTRODUCTION TO SLACK AND HOLD TIMING ANALYSIS.mp4 10.9 MB
~Get Your Files Here !/19 - BASICS OF MOS TRANSISTOR/002 GATE VOLTAGE AND ACCUMULATION OF NEGATIVE CHARGE.mp4 10.1 MB
~Get Your Files Here !/20 - SETUP & HOLD TIMING ANALYSIS/001 INITIAL TIMING ANALYSIS AND INTRODUCTION TO FLOP SETUP TIME.mp4 9.8 MB
~Get Your Files Here !/18 - GENERATED CLOCKS DEFINITION AND CREATION/002 GENERATED CLOCKS USING MASTER CLOCK EDGES.mp4 9.6 MB
~Get Your Files Here !/20 - SETUP & HOLD TIMING ANALYSIS/002 SETUP TIMING ANALYSIS WITH JITTER AND REAL CLOCKS.mp4 8.9 MB
~Get Your Files Here !/18 - GENERATED CLOCKS DEFINITION AND CREATION/001 DEFINE GENERATED CLOCK FOR DIVIDE-BY-2 CIRCUIT.mp4 8.4 MB
~Get Your Files Here !/19 - BASICS OF MOS TRANSISTOR/001 INTRODUCTION TO VLSI ACADEMY.mp4 8.1 MB
~Get Your Files Here !/18 - GENERATED CLOCKS DEFINITION AND CREATION/003 GENERATED CLOCK WAVEFORM DERIVATION.mp4 7.8 MB
~Get Your Files Here !/18 - GENERATED CLOCKS DEFINITION AND CREATION/004 GENERATED CLOCK WITH SHIFTED EDGE.mp4 7.5 MB
~Get Your Files Here !/20 - SETUP & HOLD TIMING ANALYSIS/004 HOLD TIMING ANALYSIS CONCLUDED.mp4 5.5 MB
~Get Your Files Here !/10 - Static Timing Analysis With Real Clocks/003 Impact Of Unbalanced Skew On Hold Time_en.vtt 15.7 KB
~Get Your Files Here !/08 - Buffered H-Tree/001 H-Tree Buffering Observations_en.vtt 15.2 KB
~Get Your Files Here !/15 - Noise Protection Technique/003 Drive Strength_en.vtt 15.1 KB
~Get Your Files Here !/01 - Physical Design Flow Overview/001 Floor-Planning Steps_en.vtt 15.1 KB
~Get Your Files Here !/02 - Floorplanning/003 Power Planning_en.vtt 15.0 KB
~Get Your Files Here !/08 - Buffered H-Tree/004 H-Tree Clock Buffers And Pulse Width Check_en.vtt 14.5 KB
~Get Your Files Here !/03 - Placement/002 Optimize Placement Using Estimated Wire Length And Capacitance_en.vtt 14.4 KB
~Get Your Files Here !/13 - Tolerable Glitch Heights and Introduction to AC Noise Margin/001 Impacts Of Glitch_en.vtt 14.3 KB
~Get Your Files Here !/12 - Glitch Examples And Factors Affecting Glitch Height/003 Factors Affecting Glitch Height - Aggressor Drive Strength_en.vtt 14.2 KB
~Get Your Files Here !/05 - Clock Tree Synthesis - Introduction And Quality Check Parameters/004 Power And Crosstalk Quality Check_en.vtt 14.1 KB
~Get Your Files Here !/12 - Glitch Examples And Factors Affecting Glitch Height/002 Glitch Discharge With High Drive Strength PMOS Transistor_en.vtt 14.1 KB
~Get Your Files Here !/20 - SETUP & HOLD TIMING ANALYSIS/001 INITIAL TIMING ANALYSIS AND INTRODUCTION TO FLOP SETUP TIME_en.vtt 14.0 KB
~Get Your Files Here !/05 - Clock Tree Synthesis - Introduction And Quality Check Parameters/001 Introduction To Clock Tree Synthesis_en.vtt 13.9 KB
~Get Your Files Here !/12 - Glitch Examples And Factors Affecting Glitch Height/001 Basic Crosstalk Glitch Example_en.vtt 13.8 KB
~Get Your Files Here !/12 - Glitch Examples And Factors Affecting Glitch Height/004 Factors Affecting Glitch Height - Conclusion_en.vtt 13.7 KB
~Get Your Files Here !/16 - Routing And Design Rule Check (DRC)/002 Design Rule Check_en.vtt 13.7 KB
~Get Your Files Here !/02 - Floorplanning/004 Pin Placement And Logical Cell Placement Blockage_en.vtt 13.6 KB
~Get Your Files Here !/19 - BASICS OF MOS TRANSISTOR/002 GATE VOLTAGE AND ACCUMULATION OF NEGATIVE CHARGE_en.vtt 13.6 KB
~Get Your Files Here !/01 - Physical Design Flow Overview/003 Clock Net Shielding_en.vtt 13.6 KB
~Get Your Files Here !/06 - H-Tree/001 H-Tree Algorithm And Skew Check_en.vtt 13.6 KB
~Get Your Files Here !/10 - Static Timing Analysis With Real Clocks/001 Static Timing Analysis With Real Clocks_en.vtt 13.6 KB
~Get Your Files Here !/09 - Clock Tree Optimization Checklist/001 Optimization Checklist_en.vtt 13.4 KB
~Get Your Files Here !/11 - Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP/004 Lower Supply Voltage_en.vtt 13.4 KB
~Get Your Files Here !/05 - Clock Tree Synthesis - Introduction And Quality Check Parameters/002 Duty Cycle And Latency Check_en.vtt 13.4 KB
~Get Your Files Here !/10 - Static Timing Analysis With Real Clocks/002 Impact Of Unbalanced Skew On Setup Time_en.vtt 13.4 KB
~Get Your Files Here !/05 - Clock Tree Synthesis - Introduction And Quality Check Parameters/003 Latency And Power Check_en.vtt 13.4 KB
~Get Your Files Here !/07 - Clock Tree Modelling and Observations/002 Clock Tree Building_en.vtt 13.3 KB
~Get Your Files Here !/02 - Floorplanning/002 Concept of Pre-placed Cells_en.vtt 13.3 KB
~Get Your Files Here !/06 - H-Tree/003 H-Tree Latency And Power Check_en.vtt 13.3 KB
~Get Your Files Here !/06 - H-Tree/002 H-Tree Pulse Width And Duty Cycle Check_en.vtt 13.3 KB
~Get Your Files Here !/03 - Placement/001 Netlist Binding And Placement_en.vtt 13.2 KB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/001 Setup Time Analysis And Introduction To Flip-Flop Setup Time_en.vtt 13.2 KB
~Get Your Files Here !/08 - Buffered H-Tree/003 CMOS Inverter PMOSNMOS Matching Switching Resistance Solution_en.vtt 13.2 KB
~Get Your Files Here !/01 - Physical Design Flow Overview/002 Netlist Binding And Placement Optimization_en.vtt 13.1 KB
~Get Your Files Here !/14 - Crosstalk Delta Delay Analysis/002 Setup Timing Analysis Using Real Clocks_en.vtt 13.1 KB
~Get Your Files Here !/09 - Clock Tree Optimization Checklist/002 Leakage Current Reduction Technique_en.vtt 13.1 KB
~Get Your Files Here !/11 - Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP/002 Dominant Lateral Capacitance_en.vtt 13.1 KB
~Get Your Files Here !/07 - Clock Tree Modelling and Observations/003 Clock Tree Observations_en.vtt 13.0 KB
~Get Your Files Here !/08 - Buffered H-Tree/005 Dynamic Power And Short Circuit Power_en.vtt 13.0 KB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/004 Data Slew Check_en.vtt 13.0 KB
~Get Your Files Here !/19 - BASICS OF MOS TRANSISTOR/004 IMPACT OF SUBSTRATE POTENTIAL ON THRESHOLD VOLTAGE (VT)_en.vtt 12.9 KB
~Get Your Files Here !/07 - Clock Tree Modelling and Observations/001 Clock Tree Modelling_en.vtt 12.8 KB
~Get Your Files Here !/18 - GENERATED CLOCKS DEFINITION AND CREATION/002 GENERATED CLOCKS USING MASTER CLOCK EDGES_en.vtt 12.8 KB
~Get Your Files Here !/01 - Physical Design Flow Overview/004 Route - DRC Clean - Parasitics Extraction - Final STA_en.vtt 12.7 KB
~Get Your Files Here !/08 - Buffered H-Tree/002 H-Tree Pulse Width Check And Issues With Regular Buffers_en.vtt 12.6 KB
~Get Your Files Here !/20 - SETUP & HOLD TIMING ANALYSIS/003 INTRODUCTION TO SLACK AND HOLD TIMING ANALYSIS_en.vtt 12.6 KB
~Get Your Files Here !/18 - GENERATED CLOCKS DEFINITION AND CREATION/001 DEFINE GENERATED CLOCK FOR DIVIDE-BY-2 CIRCUIT_en.vtt 12.6 KB
~Get Your Files Here !/14 - Crosstalk Delta Delay Analysis/001 Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction_en.vtt 12.6 KB
~Get Your Files Here !/15 - Noise Protection Technique/002 Spacing_en.vtt 12.5 KB
~Get Your Files Here !/17 - Parasitics Extraction/001 Introduction To IEEE 1481-1999 SPEF Format_en.vtt 12.5 KB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/003 Multiple Clock Timing Analysis And Introduction To Data Slew Check_en.vtt 12.5 KB
~Get Your Files Here !/02 - Floorplanning/001 Utilization Factor And Aspect Ratio_en.vtt 12.5 KB
~Get Your Files Here !/16 - Routing And Design Rule Check (DRC)/001 Introduction To Maze Routing - Lee's Algorithm_en.vtt 12.4 KB
~Get Your Files Here !/19 - BASICS OF MOS TRANSISTOR/001 INTRODUCTION TO VLSI ACADEMY_en.vtt 12.4 KB
~Get Your Files Here !/13 - Tolerable Glitch Heights and Introduction to AC Noise Margin/004 Justification Of Load Impact And Conclusion_en.vtt 12.3 KB
~Get Your Files Here !/13 - Tolerable Glitch Heights and Introduction to AC Noise Margin/002 Tolerable Glitch Heights Using DC Noise Margin_en.vtt 12.2 KB
~Get Your Files Here !/19 - BASICS OF MOS TRANSISTOR/003 N-CHANNEL FORMATION BETWEEN SOURCE AND DRAIN_en.vtt 12.1 KB
~Get Your Files Here !/03 - Placement/003 Optimize Placement Continued_en.vtt 12.1 KB
~Get Your Files Here !/17 - Parasitics Extraction/002 SPEF Header Description, Physical Design Flow Conclusion And What Next !!_en.vtt 11.9 KB
~Get Your Files Here !/14 - Crosstalk Delta Delay Analysis/003 Crosstalk Delta Delay - Aggressor Victim Switching In Same Direction_en.vtt 11.7 KB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/002 Setup Timing Analysis With Multiple Clocks_en.vtt 11.7 KB
~Get Your Files Here !/15 - Noise Protection Technique/001 Shielding_en.vtt 11.6 KB
~Get Your Files Here !/18 - GENERATED CLOCKS DEFINITION AND CREATION/003 GENERATED CLOCK WAVEFORM DERIVATION_en.vtt 11.4 KB
~Get Your Files Here !/11 - Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP/001 Introduction_en.vtt 11.1 KB
~Get Your Files Here !/14 - Crosstalk Delta Delay Analysis/004 Impact Of Crosstalk Delta Delay On Hold Timing_en.vtt 11.1 KB
~Get Your Files Here !/13 - Tolerable Glitch Heights and Introduction to AC Noise Margin/003 AC Noise Margin_en.vtt 11.1 KB
~Get Your Files Here !/20 - SETUP & HOLD TIMING ANALYSIS/002 SETUP TIMING ANALYSIS WITH JITTER AND REAL CLOCKS_en.vtt 11.1 KB
~Get Your Files Here !/11 - Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP/003 Noise Margin Voltage Parameters_en.vtt 10.7 KB
~Get Your Files Here !/05 - Clock Tree Synthesis - Introduction And Quality Check Parameters/005 Glitch Quality Check_en.vtt 10.1 KB
~Get Your Files Here !/18 - GENERATED CLOCKS DEFINITION AND CREATION/004 GENERATED CLOCK WITH SHIFTED EDGE_en.vtt 10.1 KB
~Get Your Files Here !/09 - Clock Tree Optimization Checklist/003 Optimized Clock Tree Power And Latency Check_en.vtt 9.0 KB
~Get Your Files Here !/20 - SETUP & HOLD TIMING ANALYSIS/004 HOLD TIMING ANALYSIS CONCLUDED_en.vtt 6.7 KB
~Get Your Files Here !/Bonus Resources.txt 386 bytes
Get Bonus Downloads Here.url 182 bytes

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